? 2005 fairchild semiconductor corporation ds500375 www.fairchildsemi.com may 2000 revised january 2005 nc7wbd3306 tinylogic ? uhs 2-bit low power bus switch with level shifting nc7wbd3306 tinylogic ? uhs 2-bit low power bus switch with level shifting general description the nc7wbd3306 is a 2-bit ultra high-speed cmos fet bus switch with enhanced level shifting circuitry and with ttl-compatible active low control inputs. the low on resistance of the switch allows inputs to be connected to outputs with minimal propagation delay and without gener- ating additional ground bounce noise. the device is orga- nized as a 2-bit switch with independent bus enable (oe ) controls. when oe is low, the switch is on and port a is connected to port b. when oe is high, the switch is open and a high-impedance state exists between the two ports. reduced voltage drive to the gate of the fet switch permits nominal level shifting of 5v to 3v through the switch. control inputs tolerate voltages up to 5.5v indepen- dent of v cc . features space saving us8 surface mount package micropak ? pb-free leadless package typical 3 ? switch resistance at 5.0v v cc , v in = 0v level shift facilitates 5v to 3.3v interfacing minimal propagation delay through the switch power down high impedance input/output zero bounce in flow through mode ttl compatible active low control inputs control inputs are overvoltage tolerant ordering code: pb-free package per jedec j-std-020b. tinylogic ? is a registered trademark of fairchild semiconductor corporation. micropak ? is a trademark of fairchild semiconductor corporation. product package description supplied as order package code number number top mark NC7WBD3306K8X mab08a wb6d 8-lead us8, jedec mo-187, variation ca 3.1mm wide 3k units on tape and reel nc7wbd3306l8x (preliminary) mac08a p7 pb-free 8-lead micropak, 1.6 mm wide 5k units on tape and reel
www.fairchildsemi.com 2 nc7wbd3306 logic diagram pin descriptions function table h = high logic level l = low logic level connection diagrams (top view) pin one orientation diagram aaa represents product code top mark - see ordering code note: orientation of top mark determines pin one location. read the top product code mark left to right, pin one is the lower left pin (see diagram). pad assignments for micropak (top thru view) pin name description a bus a switch i/o b bus b switch i/o oe bus enable input bus enable input (oe )function l b connected to a h disconnected
3 www.fairchildsemi.com nc7wbd3306 absolute maximum ratings (note 1) recommended operating conditions (note 3) note 1: the ?absolute maximum ratings? are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum ratings. the ?recommended operating conditions? table will define the conditions for actual device operation. note 2: the input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. note 3: unused logic inputs must be held high or low. they may not float. dc electrical characteristics note 4: measured by the voltage drop between a and b pins at the indicated current through the switch. on resistance is determined by t he lower of the voltages on the two (a or b) pins. note 5: per ttl driven input (v in = 3.4v, control input only). a and b pins do not contribute to i cc . supply voltage (v cc ) ? 0.5v to + 7.0v dc switch voltage (v s ) ? 0.5v to + 7.0v dc output voltage (v in ) (note 2) ? 0.5v to + 7.0v dc input diode current (i ik ) v in < 0v ? 50 ma dc output (i out ) sink current 128 ma dc v cc or ground current (i cc /i gnd ) 100 ma storage temperature range (t stg ) ? 65 c to + 150 c junction temperature under bias (t j ) + 150 c junction lead temperature (t l ) (soldering, 10 seconds) + 260 c power dissipation (p d ) @ + 85 c250 mw supply operating (v cc ) 4.5v to 5.5v control input voltage (v in ) 0v to 5.5v switch input voltage (v in ) 0v to 5.5v switch output voltage (v out ) 0v to 5.5v operating temperature (t a ) ? 40 c to + 85 c input rise and fall time (t r , t f ) control input 0 ns/v to 5 ns switch i/o 0 ns/v to dc thermal resistance ( ja )250 c/w symbol parameter v cc t a = ? 40 c to + 85 c units conditions (v) min typ max v ik clamp diode voltage 4.5 ? 1.2 v i in = ? 18 ma v ih high level input voltage 4.5 to 5.5 2.0 v v il low level input voltage 4.5 to 5.5 0.8 v v oh high level output voltage 4.5 to 5.5 see figure 3 v v in = v cc i in input leakage current 5.5 1.0 a0 v in 5.5v i off power off leakage current 5.5 1.0 a0 a, b v cc r on switch on resistance 4.5 3 7 ? v in = 0v, i in = 64 ma (note 4) 4.5 3 7 v in = 0v, i in = 30 ma 4.5 15 50 v in = 2.4v, i in = 15 ma i cc quiescent supply current 5.5 v in = v cc or gnd, i out = 0 1.1 1.5 ma oe 1 = oe 2 = gnd 10 aoe 1 = oe 2 = v cc ? i cc increase in i cc per input 5.5 1 2.5 ma v in = 3.4v, i o = 0, one control (note 5) input only, other oe = v cc
www.fairchildsemi.com 4 nc7wbd3306 ac electrical characteristics note 6: this parameter is guaranteed. the bus switch contributes no propagation delay other than the rc delay of the typical on resista nce of the switch and the 50 pf load capacitance, when driven by an ideal voltage source (zero output impedance). the specified limit is calculat ed on this basis. capacitance ac loading and waveforms input driven by 50 ? source terminated in 50 ? c l includes load and stray capacitance input prr = 1.0 mhz; t w = 500 ns figure 1. ac test circuit figure 2. ac waveforms t a = ? 40 c to + 85 c, symbol parameter v cc c l = 50 pf, ru = rd = 500 ? units conditions figure (v) min typ max number t phl , propagation delay bus to bus 4.5 to 5.5 0.25 ns v i = open figures 1, 2 t plh (note 6) t pzl , output enable time 4.5 to 5.5 1.0 3.5 5.8 ns v i = 7v for t pzl figures 1, 2 t pzh v i = 0v for t pzh t plz , output disable time 4.5 to 5.5 0.8 3.5 4.8 ns v i = 7v for t plz figures 1, 2 t phz v i = 0v for t phz symbol parameter typ max units conditions c in control pin input capacitance 2.5 pf v cc = 0v c i/o (off) port off capacitance 6 pf v cc = 5.0v = oe c i/o (on) port on capacitance 12 pf v cc = 5.0v, oe = 0v
5 www.fairchildsemi.com nc7wbd3306 dc characteristics figure 3. typical high level output voltage vs. supply voltage
www.fairchildsemi.com 6 nc7wbd3306 tape and reel specification tape format for us8 tape dimensions inches (millimeters) tape format for micropak tape dimensions inches (millimeters) package tape number cavity cover tape designator section cavities status status leader (start end) 125 (typ) empty sealed k8x carrier 250 filled sealed trailer (hub end) 75 (typ) empty sealed package tape number cavity cover tape designator section cavities status status leader (start end) 125 (typ) empty sealed l8x carrier 250 filled sealed trailer (hub end) 75 (typ) empty sealed
7 www.fairchildsemi.com nc7wbd3306 tape and reel specification (continued) reel dimensions inches (millimeters) tape size abcdn w1 w2 w3 8 mm 7.0 0.059 0.512 0.795 2.165 0.331 + 0.059/ ? 0.000 0.567 w1 + 0.078/ ? 0.039 (177.8) (1.50) (13.00) (20.20) (55.00) (8.40 + 1.50/ ? 0.00) (14.40) (w1 + 2.00/ ? 1.00)
www.fairchildsemi.com 8 nc7wbd3306 physical dimensions inches (millimeters) unless otherwise noted 8-lead us8, jedec mo-187, variation ca 3.1mm wide package number mab08a
9 www.fairchildsemi.com nc7wbd3306 tinylogic ? uhs 2-bit low power bus switch with level shifting physical dimensions inches (millimeters) unless otherwise noted (continued) pb-free 8-lead micropak, 1.6 mm wide package number mac08a (preliminary) fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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